A lightweight Python-based GPU architecture simulator that demonstrates how parallel threads, registers, memory, and instructions work on a GPU.
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Oct 27, 2026 - Python
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simt
Here are 23 public repositories matching this topic...
SIMT GPU warp execution simulator tracking active thread divergence masks, reconvergence points, and warp vote intrinsics (__ballot_sync, __all_sync, __any_sync).
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Sep 9, 2026 - Python
SIMT GPU warp execution simulator tracking active thread divergence masks, reconvergence points, and warp vote intrinsics (__ballot_sync, __all_sync, __any_sync).
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Sep 9, 2026 - Python
Implementation of a custom GPU ISA microarchitecture called GBox16 based around NVIDIA and AMD microarchitectures
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Feb 27, 2023 - VHDL
A SpinalHDL-based GPGPU for flexible architecture exploration.
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Aug 9, 2026 - Scala
High-performance Discrete Fourier Transform (DFT) implementation using NVIDIA CUDA with CPU vs GPU benchmarking.
benchmarking dft cpp parallel-computing cuda gpgpu fourier fft fourier-series fourier-analysis fourier-transform gpgpu-physics simt
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Dec 21, 2025 - C++
Four single-cycle Verilog processor cores from scratch — 16-bit MIPS-lite, 32-bit CISC (x86-style), 32-bit RISC (ARM-style), and a 32-bit SIMT GPU — with full sim setup, FPGA constraints, and microarchitecture deep-dive docs
cpu fpga gpu processor rtl verilog vivado computer-architecture risc icarus-verilog hdl basys3 cisc simt
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May 18, 2026 - Verilog
Twelve CUDA-style kernel puzzles on a simulated GPU. Write a kernel, pick the launch, and see warps, divergence, memory coalescing, bank conflicts, atomics and data races, graded against a par time. Built with Claude Code.
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Nov 2, 2026 - TypeScript
Tiny tensor compiler: one tensor program compiled to a GPU simulator (tiny-gpu) and a systolic-array TPU (tiny-tpu), checked bit-exact against numpy.
react compiler webassembly rtl astro matrix-multiplication int8 verilator tpu pyodide simt deep-learning-compiler tensor-compiler systolic-array gpu-simulator compiler-education
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Oct 27, 2026 - Python
Four-warp, eight-lane programmable SIMT processor with scoreboarding, divergence, banked memory, differential verification, and an ASIC RTL-to-GDS flow.
asic fpga gpgpu systemverilog computer-architecture gpu-architecture design-verification rtl-design simt rtl-to-gds
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Sep 27, 2026 - SystemVerilog
BradVector — the Brad Devices GPU/accelerator ISA: spec, reference RTL, and toolchain
toolchain gpu assembly wasm isa instruction-set-architecture simt bradvector bradverse reference-rtl
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Oct 20, 2026 - C
⚡ Ultra-high-throughput GPU Vector Search Engine with Warp-Cooperative HNSW, Stride-257 Shared-Memory IVF-PQ ADC, Rust host orchestration, and a real-time 3D WebGL visualizer.
rust threejs gpu nextjs websockets cuda pytorch nearest-neighbor-search ann hnsw vector-search vector-database simt ivf-pq
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Aug 31, 2026 - Rust
Browser game for learning CUDA: a simulated GPU runs your kernels warp by warp
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Nov 2, 2026 - TypeScript
Review of the paper A Formal Analysis of the NVIDIA PTX Memory Consistency Model
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Nov 8, 2024 - TeX
Repository of the lab8 assignment for the Parallel Programming course.
gpu cuda multithreading warp spatial-locality simt streaming-multiprocessor computational-kernel temporal-locality registers-per-thread 2d-blocks cuda-device-synchronization
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Jul 3, 2025 - Cuda
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Mar 5, 2022 - C++
Vortex, the open-source RISC-V GPGPU, taken as a black box
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Sep 28, 2026
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May 17, 2026 - Verilog
A deterministic functional and cycle-stepped pipeline-accurate SIMT GPU architecture simulator modeling the synthetic GV-SIM32 ISA.
gpu computer-architecture instruction-set-simulator cpp20 performance-modeling hardware-simulation simt gpu-simulator
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Jul 25, 2026 - C++
EPFL CS-550 project report
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Jan 9, 2025 - TeX
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