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Phase 9: iCE40 FPGA synthesis, UART top level and timing - #4

Merged

deaneeth merged 2 commits into

mainfrom

feat/phase-9-fpga

Oct 27, 2026

Merged

Phase 9: iCE40 FPGA synthesis, UART top level and timing#4
deaneeth merged 2 commits into
mainfrom
feat/phase-9-fpga

Commits on Oct 27, 2026
- feat: Phase 9 FPGA synthesis for the iCE40UP5K
  deaneeth
  committed
  42606b2
- fix: create the FPGA build directory before writing the CI summary
  deaneeth
  committed
  65c903f