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Phase 9: iCE40 FPGA synthesis, UART top level and timing - #4

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deaneeth merged 2 commits into
mainfrom
feat/phase-9-fpga
Oct 27, 2026
Merged

Phase 9: iCE40 FPGA synthesis, UART top level and timing#4
deaneeth merged 2 commits into
mainfrom
feat/phase-9-fpga

fix: create the FPGA build directory before writing the CI summary

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