ternary-computer

SBTCVM is a virtual machine implementation of a balanced ternary (base 3) computer. Features several compiled languages for ternary software development.

sparse ternary AI stack enabling efficient frontier intelligence without hyperscaler-scale infrastructure.

[no longer supported, please see SBTCVM-Gen2-9] Simple Balanced Ternary Computer Virtual Machine: Mark 2 is a simple Balanced Ternary VM programmed in python and Pygame.

Pure Rust engine for BitNet LLMs — Conversion, Inference, Training and Research. With streaming and GPU/CPU support

A virtual machine and toolchain for a MIPS-like architecture based on balanced ternary arithmetic

A virtual ternary OISC machine (One Instruction Set Computer) inspired by 1950s Soviet hardware

Termite is a virtual machine for a ternary-based RISC CPU architecture.

Tera - A simulated ternary (base 3) CPU, assembly language, assembler and decompiler. Uses trytes made up of 9 trits rather than bytes of 8 bits.

A translator to translate RV32I to REBEL-6. Includes custom assemblers to output RV32I (and hopefully soon REBEL-6) MRCS-readable object files, and assembly level simulators to simulate RV32I and REBEL-6 assembly code execution

This REPO exists to explore the idea of implementing ternary systems to software and hopefully hardware

Simple Balanced Ternary Computer Virtual Machine: Mark 2 is a simple Balanced Ternary VM programmed in python and Pygame.

A web puzzle game that rebuilds the computer from scratch in balanced ternary

Balanced ternary logic SoC with CPU, memory controllers, and complete synthesis flow for silicon fabrication

This repository aims to design a ternary processor that breaks away from the von Neumann architecture; by incorporating an in-memory computing approach, it offers a potential computer design solution for future artificial intelligence applications.

SBTNET is a system for packet-switched balanced ternary computer networking.

First public release of the QSOL Unified Field Framework. Includes sexagesimal, trinary, and codon mapping modules, microtonal tuning utilities, and complete Zenodo/QAInN integration. DOI: 10.5281/zenodo.17520187 License: CC BY 4.0 Motto: Small is Beautiful. Fast is Holy. Transparent by Design

A poorly implemented VM with a MIPS-style architecture based on balanced ternary arithmetic

[3/3] An Experimental Ternary (Base-3) CPU emulator written in Rust, focusing on the implementation of a 27-trit balanced ternary architecture. Driven by non-binary logic and trit-based arithmetic.

Balanced Ternary Abacus | Heisanban