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Phase 7: datapath, hazard lab and programs views - #1

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deaneeth merged 10 commits into
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feat/phase-7-views
Oct 26, 2026
Merged

deaneeth merged 10 commits into
mainfrom
feat/phase-7-views

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Summary

Phase 7 adds the remaining views to the /app page, behind level tabs:

  • L1 Datapath: an SVG of the single-cycle datapath. The wires the retired instruction uses are highlighted and labelled with real operand and result values.
  • L3 Hazard lab: eight short programs, one per hazard kind. Each runs on the pipeline with forwarding on and off, and on the single-cycle core, with cycles, stalls and flushes compared.
  • L4 Programs: every preset across both cores, with CPI, PASS/FAIL, and a data-memory access heatmap.
  • Theme toggle: light and dark, which restores the saved choice on reload.

The datapath reads operand values from a single-cycle run of the same program, since a pipeline run does not expose per-instruction operands. Both cores compute the same architecture, so the values match.

Verification

  • pnpm test: 67 Vitest tests. phase7.test.ts runs the datapath values, hazard behaviour and comparison results against the WASM core.
  • pnpm test:e2e: 9 Playwright tests against the production build, including phone-width layout with no horizontal scroll.
  • pnpm lint, pnpm typecheck, pnpm build: clean.
  • Python golden suite (333), RTL lint: unchanged and passing.

Notes

  • Clock speed is not modelled yet. The programs view reports cycles; the FPGA numbers (Phase 9) will turn them into time.
  • Docs: CONTEXT.md gains the Phase 6 and Phase 7 status and gotchas; docs/ARCHITECTURE.md has a views section.

Python reference model (decode/encode/disasm, ISS with RVFI-lite retire
records, CLI), TinyCPU memory-map linker script and riscv-tests environment,
sw Makefile, five asm example programs with pinned output and instret,
GNU objdump cross-check, generated web/src/lib/isa.ts, and CI steps.
The ISS passes all 40 rv32ui-p-* tests.
RTL building blocks (alu, imm_gen, branch_unit, lsu, decoder, regfile,
csr_counters, mmio, mem_comb), core_single and tiny_cpu_top with an RVFI-lite
retire bus and memory loader. Per-block cocotb suites, a lockstep test against
the golden ISS over all riscv-tests and programs plus fault cases, lint script,
cocotb runner, CI wiring and docs/ARCHITECTURE.md.
core_pipe (IF/ID/EX/MEM/WB with taken-branch flush, precise faults and
halt), mem_sync with write-first read, CORE="PIPE" in tiny_cpu_top and a
uniform per-stage debug bus on both cores. Adds the Prog mini-assembler and
dynamic RAW-hazard checker, hazard-free program set, a shared lockstep
library and a pipeline lockstep suite with an exact cycle-count check.
wasm/harness.cpp owns both Verilated models of tiny_cpu_top (SINGLE and PIPE,
distinct prefixes) behind one TinyCpuSim. build.sh builds the module and
enforces a 400 KB gzipped budget (77 KB today). test.mjs checks every golden
fixture on both cores, forwarding on and off, against the Python ISS: console,
registers, data memory, retire-stream digest and pipeline-model cycle counts.
Adds a hazard-dense fixture, the only one where the forwarding pin is
observable. docs/STATE_SCHEMA.md defines the JavaScript contract.
Adds the /app page: an RV32I assembler (two passes, byte-identical to GNU as/ld
on 26 sources), a disassembler, typed CycleState mirror, runner and run model,
and React views for the source, pipeline, cycle controls, registers, data
memory, console and statistics. Five presets run on the WASM core in tests.
Vitest unit and integration tests and Playwright smoke tests; CI runs both.
Adds the remaining app views behind level tabs on /app:
- L1 datapath: SVG of the single-cycle datapath with the wires the retired
  instruction uses highlighted and labelled with real operand and result values.
- L3 hazard lab: eight programs, one per hazard kind, each run on the pipeline
  with forwarding on and off and on the single-cycle core.
- L4 programs: every preset compared across cores, with CPI, PASS/FAIL, and a
  data-memory access heatmap.
- Light/dark theme toggle that restores the saved choice.

Tests: 67 Vitest (phase7.test.ts checks datapath values, hazard behaviour and
comparison results against the WASM core) and 9 Playwright smoke tests,
including phone-width layout with no horizontal scroll.
Docs: CONTEXT.md gains the Phase 6 and Phase 7 status and gotchas.
The .gitignore exception for web/public/tiny_cpu.wasm had a trailing comment,
which git reads as part of the pattern, so the file was ignored and never
committed. The Web CI unit tests load tiny_cpu.mjs, which needs the .wasm
beside it, and failed on a clean checkout. The rule is now a plain line, and
the binary is committed next to the matching tiny_cpu.mjs.
The Golden ISS step runs with REQUIRE_RISCV_TESTS=1, so the GNU fixture
freshness test fails if riscv-none-elf-gcc is not on PATH. The toolchain was
only added to PATH inside the build step, so the golden step could not see it.
A step now appends the toolchain's bin directory to GITHUB_PATH, as the
Verilator step does.
@deaneeth
deaneeth merged commit 09612ad into main Oct 26, 2026
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