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pdr2 now takes the initial value of every flop (0, 1, or don't-care) and works in the original flop polarities, instead of assuming that all flops start at 0. The counterexample's register bits hold the real initial state, and the invariant is over the original flops; neither needs mapping back. - Pdr2_ManSolveInit( pAig, vInit, pPars ); Pdr2_ManSolve() passes NULL (all 0). Abc_NtkDarPdr2() reads the latch init values and leaves the network unchanged. - Frame 0, the intersects-init tests (MIC, inductive core, abstraction projection, invariant check), the counterexample's initial state and the abstraction simulations follow the initial values. - The gated design of the abstraction runs gates flops to their defined values (don't-care flops stay ungated); the BMC stage runs on a zero-init copy and maps its counterexample back; -q is skipped unless all initial values are 0. - -d writes the design with its initial values (AIGER 1.9 latch lines). - Designs with all-zero initial values get the same search as before. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Summary
pdr2now accepts the initial value of each flop as 0, 1 or don't-care, and solves the problem in the original flop polarities. Before this change it assumed every flop starts at 0, aspdrdoes, which had three effects:Abc_NtkToDar) complemented them, so the invariant came out with inverted literals on those flops.pdr2could report "proved" when the property fails from some initial state.undcfirst (logic; undc; st; zero) fixes the semantics, but the counterexample and the invariant then describe the transformed design. Mapping the counterexample back exists (undc -c). Mapping the invariant back does not, and it is not a substitution: the correct invariant is "the initial states, or the transformed invariant with the control flop set". That is not a clause set unless each clause is multiplied out per initialized flop.pdris unchanged.Changes
Interface
Pdr2_ManSolveInit( pAig, vInit, pPars ).vInitgives 0, 1 or 2 (don't-care) per flop;NULLmeans all 0.Pdr2_ManSolve()calls it withNULL.Abc_NtkDarPdr2()reads the initial values from the latches and converts the network without complementing anything. Afterwards the network is left exactly as it was.pdr2command now adds its dummy flop as next state 0 with initial value 0. The engine sees the same AIG as before, with all-zero initial values.Engine
Frame 0: gets unit clauses only for the flops with a defined value. The frame-0 cubes follow the same rule.
Which cubes intersect the initial states: a cube meets them unless it has a literal opposite to a flop's defined value. A literal of a don't-care flop never counts. This test is used by:
Counterexample: its register bits hold the initial state of the trace, built from:
No extra SAT call is needed, because lifting guarantees that any state in the cube works. The ternary and concrete simulations of the abstraction checks start from the same state.
Final check of the counterexample: it must start in an initial state, and
Saig_ManVerifyCexmust reproduce the failure.Designs derived inside pdr2
Abstraction runs with a reset flop: a flop with a defined value is gated to that value in the reset cycle, with AND for 0 and OR for 1. Don't-care flops are left ungated and keep the don't-care value. A counterexample from these runs takes the run's values for the don't-care flops.
BMC stage: BMC assumes all-zero initial values, so it runs on a zero-init copy, and its counterexample is mapped back. In the copy:
For all-zero designs nothing is copied.
-q(scorr): skipped unless all initial values are 0.-doutputnext init, where init is 0, 1, or the latch literal for don't-care.What happens to the counterexample and the invariant
Both describe the original circuit directly, so neither needs mapping back.
The counterexample
undc, and the same number of frames.Abc_NtkVerifyCex,Saig_ManVerifyCex,Gia_ManVerifyCex) take each flop's starting value from those bits, not from the latch's init setting. Before this change the bits were all 0, so on a design with flops initialized to 1 the counterexample checked out only on the internal complemented copy. Nowtestcex -aconfirms it on the original network.The invariant
undccontrol flop. For the original design:-dwrites the design with its initial values next to the invariant.-d, also with its initial values.Designs whose flops all start at 0 get exactly the same search, counterexamples and invariants as before.
Testing
No change on all-zero designs: the 77 IWLS'17 examples at 60 s, 4 jobs (none has a non-zero initial value). Results and solver propagation counts are identical to the previous build on all 66 examples it solves within 60 s.
Random circuits with random initial values: 3–6 flops; each flop is 0, 1 or don't-care. A local harness ran 17 pdr2 configurations on 600 circuits each, about 77% of them with non-zero initial values. Every configuration passed:
End to end: 48 variants of IWLS examples with 10% of the flops at 1, at don't-care, or both. Three routes agree on 47 of them; on the remaining one,
pdrran out of time at 30 s while bothpdr2routes proved it:pdr2on the original files;pdr2afterlogic; undc; st; zero;pdrafter the same commands.All 29 counterexamples pass
testcex -aon the original networks. All 19 proofs pass the built-in invariant verification, and their dumped designs carry the input's initial values.Side finding:
undcon a strashed network does nothing. Withoutlogicfirst, the old route silently treats don't-care values as 0, and it proved 12 of these variants that actually fail.🤖 Generated with Claude Code