Undergraduate at Nanjing University (VLSI Design & System Integration), graduating in 2027.
I work on AI accelerator architecture, hardware-software co-design, and evidence-driven RTL engineering — connecting workload mapping and scheduling with persistent AI engineering systems.
Personal website · Vulcan portfolio · Public RTL Showcase
- Nanjing University — VLSI Design & System Integration
- Campus locations: Nanjing (Year 1); Suzhou (Years 2–4)
- Expected graduation: 2027
| Period | Experience |
|---|---|
| Sep–Dec 2026 | Microsoft Research Asia (MSRA) — Research Intern, Systems Research Group, Beijing. Group website ↗ |
| Jan–May 2027 | Nanyang Technological University (NTU), Singapore — Government-Sponsored Visiting Undergraduate. Program website ↗ |
Methods: DNN mapping, inter-layer scheduling, NoC and memory-system data movement. I contribute to HyperCut and maintain a Crane reproduction lab.
With Argus AI Team, I contribute to Argus / Microsoft · original project, a persistent multi-agent runtime, its chip-design vertical, interfaces and evidence-driven evaluation.
Vulcan is an independent AI-native hardware engineering project, not part of Argus AI Team. It connects scoped RTL implementation, verification, independent review and reproducible delivery. Its public portfolio includes ANVIL E/Q, RIVET/BILLET, SABLE and ten component IPs.
| Family | Focus and public evidence |
|---|---|
| ACE-2 / ACE-3 MP | W4A8 persistent RTL dialogue and native AWQ W4A16 research. ACE-2 has accepted two-turn, four-token-per-turn simulation with 24 retained K/V layers and zero mismatches. ACE-3 has verified G128 projection and bounded FP16-boundary blocks; full-regression, full-model and hardware acceptance remain open. |
| ANVIL — Q (Quantized LLMs) / E (Multimodal Embeddings) | Synthesizable 100 MHz+ SystemVerilog accelerators verified on Intel Arria 10 GX PCIe Gen3x8 HIL with dual-track IEEE/ACM reports. Anvil-Q1 (Qwen2.5-0.5B-Instruct-AWQ, 108.48 MHz) & Anvil-Q2 (Qwen2.5-1.5B-Instruct-AWQ, 1/2/4-bank + INT8 KV-Cache, 101.39 MHz); Anvil-E1/E2/E3 (google/embeddinggemma-2 Text, Vision+Text & Audio+Vision+Text Trimodal, 107.31–111.63 MHz). |
ACE organization mirrors: ACE-2 · ACE-3.
RIVET & BILLET are presented together, with generations kept inside their repositories:
| Family | Product lines |
|---|---|
| RIVET | A — AES/GCM, key/context management and DMA · H — SHA/HMAC and saved hashing contexts |
| BILLET | T — FFT/IFFT and spectral analysis · F — programmable FIR/IIR filtering |
All 12 generations across RIVET-A (A1..A3), RIVET-H (H1..H3), BILLET-T (T1..T3), and BILLET-F (F1..F3) achieve 100 MHz+ Quartus 17.1 STA timing closure (107.47–210.22 MHz) and physical Intel Arria 10 GX PCIe Gen3x8 HIL verification, accompanied by monolingual dual-track academic and developer PDF reports. SABLE provides 4-stream reliable message transport, and Vulcan Showcase indexes all 17 verified chips and 10 reusable SystemVerilog IP cores.
64-Point FFT: folded streaming SDF, Q1.15, XSim/Python co-verification and routed Virtex-7 results. Two-Stage CMOS Op-Amp: TSMC 0.18 μm Miller compensation with Spectre AC/DC/transient verification.
- HyperCut: Fast Inter-Layer Scheduling via Directed Hypergraph and Early Filtering
https://arxiv.org/abs/2608.19296— Early filtering and hypergraph-based inter-layer scheduling for tiled DNN accelerators. - Argus: A General-Purpose Agentic Reasoning Runtime for Long-Horizon Tasks
https://arxiv.org/abs/2608.05144— A persistent, self-evolving runtime for long-horizon agentic reasoning.
- Personal website
https://ahappend.github.io/ - arXiv Author Profile
https://arxiv.org/a/0009-0002-5674-7448.html - ORCID
https://orcid.org/0009-0002-5674-7448 - X
https://x.com/hapouterwall - Instagram
https://instagram.com/hapouterwall - YouTube
https://www.youtube.com/@hapouterwall - Linktree
https://linktr.ee/sufeng_guo
Python C / basic C++ TypeScript SystemVerilog Verilog React Linux
- Nanjing University email
sufeng_guo@smail.nju.edu.cn - Gmail
hapouterwall@gmail.com - QQ Mail
sufeng_guo@qq.com