[tvami]

ESA ECal/HCal dev from Oct 2026.

• Fixed CHARGE_TIMESCAN failing on the Si ROC by setting CALIB_2V5 and CHOICE_CINJ only for the SiPM ROC in charge_timescan.cxx (b81c8a3)
• Fixed pftool exiting with "basic_string: construction from null" and rc 127 when a -s script ran out with no terminal attached; end of input now leaves the menus cleanly in src/pflib/menu/Menu.cc (a485902)
• Fixed TOA_SCAN and TOT_SCAN failing on the Si ROC by setting CHOICE_CINJ only for the SiPM ROC (cd22934)
• Fixed aligning one layer breaking the readout of the other layers on the same Bittware card: PHASE_WORD_ALIGN broadcasts link resets, which made every ECON-D re-snapshot and lose word lock. It now sets ALIGNER.GLOBAL_SNAPSHOT_EN = 0 after a successful word align (cb8cf3d)
• Kept the global GTH/TX resets in BWOptoLink::reset_link, since pfinit's buffer bypass only completes with them; bbd63c8 removed them and is reverted by b8ec2f4
• Fixed ROC::readPage and writePage corrupting registers on an I2C retry: the R3 address auto-increments, so each attempt now re-points to the start of its chunk, and the retry counter actually counts (470f0e6)
• Added calibration sets: one config/calib/<target>/<date>.yaml per target with a shared base file, per-ROC settings, masks, the FC calib delay and the expected pedestal. A calib: line in the target yaml names the active set, ROC APPLY_CALIB loads it, and ana/calib/make_calib.py builds it from the settings files the tasks write (1cd8ef8)
• Added the ESA 2026-10-28 calibration sets for ECal L2 and L3 and for HCal: pedestal leveling, TOA_SCAN and TOT_SCAN settings, and masks on high-pedestal channels (2b64c6e)
• Added TASKS CHECK_PEDESTAL, which compares a pedestal run with the calibration set's expected pedestal per channel (735b7e9)

Tested at ESA on CaloBittware: ECal L1 to L3 alignment (all eRx at bx 20) and pedestals; L2 and L3 leveled to about 200 ADC with a channel spread of about 5 ADC and no frozen channels. HCal alignment and pedestal on datadev_2.