GitHub - Elkwizard/ZE2Processor: A thoroughly cached and partially pipelined custom CPU for the 0=2 assembly language, designed to be run on a DE1-SoC FPGA.

Name		Name	Last commit message	Last commit date
.gitignore		.gitignore
DE1_SoC.qpf		DE1_SoC.qpf
DE1_SoC.qsf		DE1_SoC.qsf
DE1_SoC.qws		DE1_SoC.qws
DE1_SoC.sdc		DE1_SoC.sdc
DE1_SoC.srf		DE1_SoC.srf
LEDDriver.sv		LEDDriver.sv
base_half_processor_wave.do		base_half_processor_wave.do
bit_stream.sv		bit_stream.sv
bit_stream_tb_rom.mif		bit_stream_tb_rom.mif
bit_stream_wave.do		bit_stream_wave.do
cache.sv		cache.sv
cache_tb_ram.mif		cache_tb_ram.mif
cache_wave.do		cache_wave.do
clock_divider.sv		clock_divider.sv
cycle.mif		cycle.mif
emulate.js		emulate.js
factorial.mif		factorial.mif
flip.sv		flip.sv
flip_wave.do		flip_wave.do
global_ram.mif		global_ram.mif
half_processor.sv		half_processor.sv
half_processor_tb_ram.mif		half_processor_tb_ram.mif
half_processor_tb_rom.mif		half_processor_tb_rom.mif
half_processor_wave.do		half_processor_wave.do
iomap.txt		iomap.txt
jump_table.sv		jump_table.sv
jump_table_wave.do		jump_table_wave.do
lab8.sv		lab8.sv
lab8_tb.sv		lab8_tb.sv
lab8_tb_rom.mif		lab8_tb_rom.mif
lab8_wave.do		lab8_wave.do
led4.mif		led4.mif
literal_executor.sv		literal_executor.sv
nsync.sv		nsync.sv
nsync_wave.do		nsync_wave.do
opcode_executor.sv		opcode_executor.sv
opcode_executor_wave.do		opcode_executor_wave.do
opcodes.sv		opcodes.sv
processor.sv		processor.sv
processor_tb_2_rom.mif		processor_tb_2_rom.mif
processor_tb_3_rom.mif		processor_tb_3_rom.mif
processor_tb_4_rom.mif		processor_tb_4_rom.mif
processor_tb_5_rom.mif		processor_tb_5_rom.mif
processor_tb_6_rom.mif		processor_tb_6_rom.mif
processor_tb_rom.mif		processor_tb_rom.mif
processor_wave.do		processor_wave.do
ram.mif		ram.mif
ram.qip		ram.qip
ram.v		ram.v
ram_bb.v		ram_bb.v
ram_tb.sv		ram_tb.sv
ram_wave.do		ram_wave.do
rom.mif		rom.mif
rom.qip		rom.qip
rom.v		rom.v
rom_bb.v		rom_bb.v
rom_word.dot		rom_word.dot
rom_word.sv		rom_word.sv
rom_word.svg		rom_word.svg
rom_word_tb_rom.mif		rom_word_tb_rom.mif
rom_word_wave.do		rom_word_wave.do
runlab_bit_stream.do		runlab_bit_stream.do
runlab_cache.do		runlab_cache.do
runlab_flip.do		runlab_flip.do
runlab_half_processor.do		runlab_half_processor.do
runlab_jump_table.do		runlab_jump_table.do
runlab_lab8.do		runlab_lab8.do
runlab_nsync.do		runlab_nsync.do
runlab_opcode_executor.do		runlab_opcode_executor.do
runlab_processor.do		runlab_processor.do
runlab_ram.do		runlab_ram.do
runlab_rom_word.do		runlab_rom_word.do
runlab_screen_adapter.do		runlab_screen_adapter.do
runlab_timer.do		runlab_timer.do
screen_adapter.sv		screen_adapter.sv
screen_adapter_wave.do		screen_adapter_wave.do
test_io.mif		test_io.mif
timer.sv		timer.sv
timer_wave.do		timer_wave.do
userom.sh		userom.sh
watch.sh		watch.sh

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A thoroughly cached and partially pipelined custom CPU for the 0=2 assembly language, designed to be run on a DE1-SoC FPGA.

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